The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 micron and under, such as 0.18 micron, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 micron and under generates numerous problems challenging the limitations of conventional technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers, as part of "back-end" wafer processing, comprises a subtractive etching or etch back step as the primary metal patterning technique. Such methodology involves the formation of a first dielectric interlayer on a semiconductor substrate, typically doped monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region in or on the semiconductor substrate, such as a gate oxide or a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric material, such as spin-on glass (SOG) is typically deposited to fill in the gaps between the metal features and baked at an elevated temperature. The baking time is determined depending upon the particular material employed. Thereafter, another dielectric layer is deposited thereover, such as a silicon oxide derived from tetraethyl orthosilicate (TEOS) by plasma enhanced chemical vapor deposition (PECVD). Planarization, as by chemical-mechanical planarization (CMP), is then performed.
The drive to increased density and attendant shrinkage in feature size generates numerous problems. For example, as feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.50 micron and below, such as 0.375 micron, it becomes increasingly difficult to satisfactorily voidlessly fill in the interwiring spacings with a dielectric material and obtain adequate step coverage.
Hydrogen silsesquioxane (HSQ) offers many advantages for use in back-end wafer processing. HSQ is relatively carbon free, thereby rendering it unnecessary to etch back HSQ below the upper surface of the metal lines to avoid poisoned via problems. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.30 micron while still employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C., but it does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. in intermetal applications. As deposited, HSQ is considered a relatively low dielectric constant ("low k") material with a dielectric constant of about 2.9-3.0, compared to silicon dioxide grown by a thermal oxidation or chemical vapor deposition which has a dielectric constant of about 3.9-4.2. The mentioned dielectric constants are based on a scale wherein 1.0 represents the dielectric constant of air.
Other hydrogen containing low dielectric constant materials suitable for use as gap filling and/or cap layers in back-end wafer processing include but are not limited to methyl silsesquioxane (MSQ) and other organic low k materials.
However, in attempting to apply a hydrogen-containing low k material, such as HSQ, to "back-end" wafer processing as described above, particularly for gap filling, it was found that the hydrogen contained therein undesirably diffuses into the underlying dielectric interlayer during its deposition and/or during subsequent processing. Such hydrogen diffusion into the dielectric interlayer overlying active device regions formed in or on the substrate adversely affects hot carrier injection reliability which, in turn, reduces or deleteriously affects device performance.
In addition, deleterious hydrogen diffusion into the dielectric interlayer may also result upon formation and/or subsequent processing of a hydrogen containing oxide "cap" layer typically deposited over the dielectric layer prior to metal pattern formation and gap filling.
There exists a need for semiconductor technology enabling the use of low dielectric constant gap fill layers, such as HSQ, without adverse impact on hot carrier injection reliability.